The present invention relates to a data bus driving circuit, and a semiconductor device and a semiconductor device including the data bus driving circuit. In particular, the present invention relates to a data bus driving circuit suitable for reducing power consumption in a data bus without degrading the processing performance, and a semiconductor device and a semiconductor memory device including the data bus driving circuit.
Due to the miniaturization of a process and increase in capacity of memories, data held in memory cells tend to be unstable. Accordingly, in order to improve the reliability of data, the number of memories having an ECC (Error Check and Correct) function for detecting storage of erroneous data and correcting the data has recently been increasing.
In a single memory and an LSI (Large Scale Integration) incorporating a memory, the capacity of the memory and the number of data bits has been increased so as to improve the processing performance of the system. Therefore, the ratio of electric power consumed in a data bus to the entire power consumption has been increasing.
A solution to the above problem is disclosed in Japanese Unexamined Patent Application Publication No. 2005-173860. In a data storage device disclosed in Japanese Unexamined Patent Application Publication No. 2005-173860, whether or not to logically invert each value of bits constituting data including main data and an error correction node is determined so as to obtain a data pattern in which power consumption is reduced during data storage processing, and the data or the inverted data thereof is written into a memory cell array based on the determination result. During data reading, when the data read out from the memory cell array is the inverted data, the inverted data is re-inverted to be restored into the original data. Thus, the current consumption is reduced.
In addition, Japanese Unexamined Patent Application Publication No. H05-334206 discloses a configuration for controlling whether or not to invert the polarity of a bit string constituting transmit data based on a result of a comparison between the transmit data and a bus signal.